`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/01/05 23:32:00 (Happy Birthday to Hongyi)
// Design Name: 
// Module Name: Acc_ALU_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module AccALU_tb();

reg  clk, rst_n;
reg  [ 2:0] i_op;
reg  [31:0] i_data;
wire [31:0] o_data;

AccALU #(
    .DataWidth('d32)
) UUT (
    .clk(clk),
    .rst_n(rst_n),
    .i_data(i_data),
    .i_op(i_op),
    .o_data(o_data)
);

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, AccALU_tb);
end

initial begin
    clk = 0; rst_n = 1;
    i_op = 3'b000; i_data = 32'b0; #7
    rst_n = 0; #20 rst_n = 1;
    @(posedge clk) #0 i_op = 3'd0; i_data = 32'd0; #20 // 0
    @(posedge clk) #0 i_op = 3'd1; i_data = 32'd8; #20 // 0 + 8 = 8
    @(posedge clk) #0 i_op = 3'd2; i_data = 32'd4; #20 // 8 - 4 = 4 
    @(posedge clk) #0 i_op = 3'd3; i_data = 32'd3; #20 // 4 * 3 = 12
    @(posedge clk) #0 i_op = 3'd4; i_data = 32'd1; #20 // 12 << 1 = 24
    @(posedge clk) #0 i_op = 3'd5; i_data = 32'd2; #20 // 24 >> 2 = 6
    @(posedge clk) #0 i_op = 3'd6; i_data = 32'd15; #20 // 15
    @(posedge clk) #0 i_op = 3'd7; i_data = 32'd45; #100 // 15 ...
    $finish(0);
end

always #10 clk = ~clk;
 
endmodule
